Theory of Operation
The linear feedback shift register is an efficient means of counting to specific number of clocks before producing a terminal count.  It is a serial in parallel out shift register whose input is fed back from an exclusive or tree. The inputs to the excusive or tree are placed at specific taps along the shift register's parallel output. If the shift register is preset to all ones, it well sequence up to 2^n - 1 states in a pseudo random sequence before returning to all ones. Note that an all zero condition will not sequence and therefore the maximum sequence acheivable is 2^n - 1.  The advantage over an arithmetic counter is speed and simplicity. For counts up to 2^100 - 1, the LFSR counter requires one to three exclusive or gates deep of maximum propagation delay. 

This implementation presets the shift register to a specific state and counts to all ones. The terminal count detects the all ones case using nand logic for small counters or counts ones shifted through for large counters. Terminal count is asserted (put into the active state) for one clock period. The preset is synchronous and counting begins after the preset is asserted prior to set up time before clock edge and then deasserted after the hold time. The counter can be made retriggerable by asserting it's own preset from terminal count or count a sequence from preset one time. The clock can be enabled or disabled for counting events. 

For more information:
"Modern Logic Design" by David Green